I2C Interrupts
- group I2C_Interrupts
Defines
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I2C_INT_MST_ON_HOLD
When Master TX FIFO is empty and no stop bit command is issued, master will hold the SCL low.
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I2C_INT_GEN_CALL
Set only when a General Call address is received and it is acknowledged.
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I2C_INT_START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.
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I2C_INT_STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.
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I2C_INT_ACTIVITY
This bit captures I2C activity and stays set until it is cleared.
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I2C_INT_RX_DONE
When the I2C is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
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I2C_INT_TX_ABRT
This bit indicates if I2C as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO.
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I2C_INT_RD_REQ
This bit is set to 1 when acting as a slave and another I2C master is attempting to read data.
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I2C_INT_TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register.
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I2C_INT_TX_OVER
Set during transmit if the transmit buffer is filled to TX FIFO depth and the processor attempts to issue another I2C command.
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I2C_INT_RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register.
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I2C_INT_RX_OVER
Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device.
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I2C_INT_RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading.
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I2C_GET_INT(INT)
Check if the input parameter is valid.
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I2C_INT_MST_ON_HOLD