I2S Interrupt Definition

group I2S_Interrupt_Definition

Defines

I2S_INT_TX_VALID BIT7

The I2S interrupt for TX valid.

I2S_INT_TX_IDLE BIT6

The I2S interrupt for TX is working, but FIFO_0 is empty.

I2S_INT_RF_EMPTY BIT5

The I2S interrupt for RX FIFO_0 is empty (MIC path).

I2S_INT_TF_EMPTY BIT4

The I2S interrupt for TX FIFO_0 is empty (SPK path).

I2S_INT_RF_FULL BIT3

The I2S interrupt for RX FIFO_0 is full (MIC path).

I2S_INT_TF_FULL BIT2

The I2S interrupt for TX FIFO_0 is full (SPK path).

I2S_INT_RX_READY BIT1

The I2S interrupt is ready to receive data (MIC path).

I2S_INT_TX_READY BIT0

The I2S interrupt is ready to send data out (SPK path).

IS_I2S_INT_CONFIG(INT)                                          (((INT) == I2S_INT_TX_IDLE) || ((INT) == I2S_INT_RF_EMPTY

) || \

((INT) ==

I2S_INT_TF_EMPTY) || ((INT) == I2S_INT_RF_FULL

) || \

((INT) ==

I2S_INT_TF_FULL) || ((INT) == I2S_INT_RX_READY

) || \

((INT) ==

I2S_INT_TX_READY) )