SPI Interrupt

group SPI_Interrupt

Defines

SPI_INT_TXE BIT0

Transmit FIFO empty interrupt.

SPI_INT_TXO BIT1

Transmit FIFO overflow interrupt.

SPI_INT_RXU BIT2

Receive FIFO underflow interrupt.

SPI_INT_RXO BIT3

Receive FIFO overflow interrupt.

SPI_INT_RXF BIT4

Receive FIFO full interrupt.

SPI_INT_MST BIT5

Multi-Master contention interrupt. (master only)

SPI_INT_FAE BIT5

The data of slave rx does not match DFS. (slave only)

SPI_INT_TUF BIT6

Transmit FIFO underflow interrupt. (slave only)

SPI_INT_RIG BIT7

CS rising edge detect interrupt. (slave only)

IS_SPI_CONFIG_IT(IT)                               (((IT) == SPI_INT_TXE

) || \

((IT) ==

SPI_INT_TXO

) || \

((IT) ==

SPI_INT_RXU

) || \

((IT) ==

SPI_INT_RXO

) || \

((IT) ==

SPI_INT_RXF

) || \

((IT) ==

SPI_INT_MST

) || \

((IT) ==

SPI_INT_FAE

) || \

((IT) ==

SPI_INT_TUF

) || \

((IT) ==

SPI_INT_RIG) )

Check if the input parameter is valid.