Clock Management

Overview

The RTL87x2G supports multiple clock sources, allowing the system and external modules to choose different clock sources to achieve the required clock frequencies.

This document introduces the clock configuration methods for the RTL87x2G chip, mainly including the following sections:

• Supported selectable clock sources: low-speed 32KHz clock, high-speed 40MHz clock, and PLL clocks.

• Clock configuration examples for different modules.

• Interfaces related to clock configuration.

The steps for clock configuration are as follows:

• Configure the frequency of the clock source.

• Select the clock source used by the system and external modules.

• Configure the necessary frequency divider for the system and external modules, and output the clock.

Note

Modifying the frequency of the clock source for one module may affect the clock for other modules using the same clock source.

Clock Source Introduction

The support of various clock sources for different modules is shown below.

The support of various clock sources for different modules

Clock Source	CPU	FMC	RTC	QDEC	WDT	TRNG	Segment LCD	Display	SDHC	PKE	Ethernet	USB	UART	I2C	Timer	Enhanced Timer	IR	SPI0 Master	SPI0 Slave
32KHz Clock	×	×	√	√	√	√	√	×	×	×	×	×	×	×	√	×	×	×	×
40MHz Clock	√	√	×	×	×	×	×	√	√	√	×	√	√	√	√	√	√	√	√
PLL Clock	√	√	×	×	×	×	×	√	√	√	PLL1	√	×	×	√	√	√	√	√

Low-Speed 32KHz Clock

1. The low-speed 32KHz clock remains active in DLPS mode.

2. The frequency of the 32KHz clock source cannot be modified.

High-Speed 40MHz Clock

1. The high-speed 40MHz clock cannot be maintained in DLPS mode.

2. The frequency of the 40MHz clock source cannot be modified.

Ultra-Fast PLL Clock

1. The ultra-fast PLL clock cannot be maintained in DLPS mode.

2. The frequency of the PLL clock source can be changed.

PLL1 Clock

1. The range of the PLL1 clock is 400M - 500MHz, with a step size of 20MHz. The current default frequency is 500MHz.

2. PLL1 clock output is shown in the figure below, and the PLL1 source frequency is CKO_PLL1_VCO.

PLL1 Clock Output

PLL1 can output four clocks, the output frequency can be generated by CKO_PLL1_VCO.

• CKO_PLL1_CPU: Can only be used as the clock source for the CPU and FMC, obtained by dividing CKO_PLL1_VCO by 1/2.

• CKO_PLL1_PERI: Can be used as the clock source for most peripherals, obtained by dividing CKO_PLL1_VCO by 1/2, 1/4, 1/5.

• CKO_PLL1_ETH: Can only be used as the clock source for Ethernet, obtained by dividing CKO_PLL1_VCO (fixed at 500MHz) by 1/2, 1/4.

• CKO_PLL1_ETH50M: Can only be used as the clock source for Ethernet, obtained by dividing CKO_PLL1_VCO (fixed at 500MHz) by 1/10.

PLL2 Clock

1. The range of the PLL2 clock is 80M - 240MHz. The current default frequency is 160MHz.

2. PLL2 clock output is shown in the figure below, and the PLL2 source frequency is CKO_PLL2_VCO.

PLL2 Clock Output

PLL2 only outputs one clock, the output frequency can be generated by CKO_PLL2_VCO.

• CKO_PLL2: It can be used as the clock source for the CPU, FMC, and Peripherals, derived through CKO_PLL2_VCO frequency division of 1/1, 1/2.

Clock Configuration Examples

CPU and FMC Clock Configuration

CPU Clock Configuration

The default CPU clock source is a 40MHz clock. To increase the clock frequency, choose CKO_PLL1_CPU and CKO_PLL2 as the clock source. The maximum CPU clock can be configured to 125MHz.

1. The CPU needs to configure the CPU clock by calling pm_cpu_freq_set() .

2. Configure the CPU clock to 125MHz.

   uint32_t actual_mhz = 0;
   pm_cpu_freq_set(125, &actual_mhz);
   

   Note

   The interface automatically implements the following configuration: PLL1 Clock is selected as 500MHz, CKO_PLL1_CPU is 250MHz. CPU selects CKO_PLL1_CPU as the clock source with a divider of 1/2.

FMC Clock Configuration

The default FMC clock source is 40MHz. To increase the clock frequency, you can choose CKO_PLL1_CPU and CKO_PLL2 as the clock source.

FMC needs to select the corresponding interface based on the specific module. Below is an example for Flash Nor.

1. Flash requires configuring the clock based on the specific Flash Nor ID by calling fmc_flash_nor_clock_switch() .

2. For Flash Nor, select FLASH_NOR_IDX_SPIC0 ID and configure the clock to 160MHz.

   uint32_t actual_mhz = 0;
   fmc_flash_nor_clock_switch(FLASH_NOR_IDX_SPIC0, 160, &actual_mhz);
   

   Note

   The interface automatically implements the following configuration: selects 160MHz for PLL2 Clock, sets CKO_PLL2 to 160MHz. SPIC0 selects CKO_PLL2 as the clock source.

Peripheral Clock Configuration

Ethernet Clock Configuration

When using the Ethernet clock, PLL1 Clock is fixed at 500MHz.

The Ethernet clock source can only select CKO_PLL1_ETH (125MHz, 250MHz) or CKO_PLL1_ETH50M (50MHz).

1. Configure the required frequency of the clock source for Ethernet by calling pm_ethernet_freq_set() .

2. Configure the Ethernet clock frequency to 125MHz (only 50MHz, 125MHz, 250MHz can be selected).

   pm_ethernet_freq_set(CLK_PLL1_SRC, 125, 125);
   

   Note

   The interface automatically implements the following configuration: PLL1 clock is set to 500MHz, CKO_PLL1_ETH is 125MHz. Parameter required_mhz is for recording purposes only.

Timer Clock Configuration

The clock source for the Timer can be selected from 32KHz clock, 40MHz clock, CKO_PLL1_PERI of PLL1 clock, CKO_PLL2 of PLL2 clock.

Currently, the interface does not support modifying the clock frequencies of PLL1 and PLL2. The PLL1 clock frequency is fixed at 500MHz, and the PLL2 clock frequency is fixed at 160MHz. CKO_PLL1_PERI can only be selected from 100MHz, 125MHz, 250MHz.

1. The Timer needs to configure the frequency of the selected clock source by calling pm_timer_freq_set() .

2. The Timer sets the frequency of CKO_PLL1_PERI to 250MHz.

   pm_timer_freq_set(CLK_PLL1_SRC, 250, 125);
   

   Note

   The interface automatically implements the following configuration: PLL1 clock selects 500MHz, CKO_PLL1_PERI = 250MHz. Parameter required_mhz is for record-keeping only.

3. The Timer calls TIM_StructInit() and TIM_TimeBaseInit(), to select CKO_PLL1_PERI as the clock source for the Timer, and set the divider to 1/2. The final output frequency is 125MHz.

   TIM_TimeBaseInitTypeDef TIM_InitStruct;
   TIM_StructInit(&TIM_InitStruct);
   TIM_InitStruct.TIM_ClockSrc = CK_PLL1_TIMER;
   TIM_InitStruct.TIM_SOURCE_DIV = TIM_CLOCK_DIVIDER_2;
   TIM_TimeBaseInit(TIMER_NUM, &TIM_InitStruct);
   

Clock Management APIs

• pm_cpu_freq_set()

• pm_cpu_freq_get()

• pm_cpu_slow_freq_set()

• fmc_flash_nor_clock_switch()

• fmc_psram_clock_switch()

• pm_display_freq_set()

• pm_display_freq_unset()

• pm_sdhc_freq_set()

• pm_sdhc_freq_unset()

• pm_pke_freq_set()

• pm_pke_freq_unset()

• pm_ethernet_freq_set()

• pm_ethernet_freq_unset()

• pm_usb_freq_set()

• pm_usb_freq_unset()

• pm_timer_freq_set()

• pm_timer_freq_unset()

• pm_enhanced_timer_freq_set()

• pm_enhanced_timer_freq_unset()

• pm_ir_freq_set()

• pm_ir_freq_unset()

• pm_spi0_master_freq_set()

• pm_spi0_master_freq_unset()

• pm_spi0_slave_freq_set()

• pm_spi0_slave_freq_unset()