PSRAM Usage Notes

The RTL8773EWE-VP is a version of the RTL8773EWE with built-in PSRAM. The built-in PSRAM model is W955D8MBYA, powered by LDO_AUX2. The corresponding pins for PSRAM are: P7_0~P7_6, SPIC1_WP#, SPIC1_SO, SPIC1_CSN, SPIC1_SI, SPIC_SCK, SPIC_HOLD#. Therefore, when using PSRAM, please do not configure these pins additionally.

PSRAM Usage Process

The SDK has encapsulated some APIs for developers to use to support this PSRAM.

1. PSRAM Initialization

• Call watch_wb_opi_psram_init().

2. PSRAM Mode Configuration and Exit

• When entering and exiting DLPS, to meet different levels of low power consumption needs, the PSRAM can be configured in the following three modes:

  • Standby: Data can be preserved

  • Half Sleep: Some data can be preserved

  • Powerdown: Data cannot be saved

When entering DLPS, you can call the interface in app_dlps_enter_callback():

bool fmc_psram_enter_lpm(FMC_PSRAM_IDX_TYPE idx, FMC_PSRAM_LPM_TYPE mode);

Configuration example:

fmc_psram_enter_lpm(FMC_PSRAM_IDX1, FMC_PSRAM_LPM_STANDBY_MODE);

fmc_psram_enter_lpm(FMC_PSRAM_IDX1, FMC_PSRAM_LPM_HALF_SLEEP_MODE);

fmc_psram_enter_lpm(FMC_PSRAM_IDX1, FMC_PSRAM_LPM_DEEP_POWER_DOWN_MODE);

When exiting DLPS, you can call the interface in app_dlps_exit_callback():

bool fmc_psram_exit_lpm(FMC_PSRAM_IDX_TYPE idx, FMC_PSRAM_LPM_TYPE mode);

Configuration example:

fmc_psram_exit_lpm(FMC_PSRAM_IDX1, FMC_PSRAM_LPM_STANDBY_MODE);

fmc_psram_exit_lpm(FMC_PSRAM_IDX1, FMC_PSRAM_LPM_HALF_SLEEP_MODE);

fmc_psram_exit_lpm(FMC_PSRAM_IDX1, FMC_PSRAM_LPM_DEEP_POWER_DOWN_MODE);

3. PSRAM Refresh Area Setting

• This PSRAM supports refreshing different areas in Standby or Half Sleep mode. You can configure the area to be refreshed before entering DLPS. The interface is:

  bool fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX_TYPE idx, FMC_PSRAM_WB_PARTIAL_ARRAY_REFRESH partial);
  

Configuration example:

fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX1, FMC_PSRAM_WB_REFRESH_FULL);

fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX1, FMC_PSRAM_WB_REFRESH_BOTTOM_1_2);

fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX1, FMC_PSRAM_WB_REFRESH_BOTTOM_1_4);

fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX1, FMC_PSRAM_WB_REFRESH_BOTTOM_1_8);

fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX1, FMC_PSRAM_WB_REFRESH_NONE);

fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX1, FMC_PSRAM_WB_REFRESH_TOP_1_2);

fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX1, FMC_PSRAM_WB_REFRESH_TOP_1_4);

fmc_psram_wb_set_partial_refresh(FMC_PSRAM_IDX1, FMC_PSRAM_WB_REFRESH_TOP_1_8);

• FMC_PSRAM_WB_REFRESH_BOTTOM_1_8: 1/8 region from the bottom upwards, starting from zero.

• FMC_PSRAM_WB_REFRESH_TOP_1_8: 1/8 region from the top downwards, starting from the highest point.

• FMC_PSRAM_WB_REFRESH_FULL: SDK default configuration.

4. PSRAM complete power-down and power-up

• If it is necessary to completely power down the PSRAM from the power source when entering DLPS, use the following interface to configure the power and Pad respectively when power-down is needed (e.g., screen off):

  • void app_pmu_handle_ldo_aux2(bool enable);
    

  • bool fmc_psram_set_pad_config_for_psram_power_off(FMC_PSRAM_IDX_TYPE idx, bool enter_lpm);
    

Note

• When resuming the use of PSRAM, it is necessary to power the Pad first, then power the ldo_aux2, and finally reinitialize the PSRAM after the necessary delay for power stabilization. The difference from FMC_PSRAM_LPM_DEEP_POWER_DOWN_MODE is that the initialization requires a strict time sequence, so the power-on display will have a delay.

Configuration example:

• Power down:

  1. app_pmu_handle_ldo_aux2(DISABLE);
     

  2. fmc_psram_set_pad_config_for_psram_power_off(FMC_PSRAM_IDX1, true);
     

• Power-on initialization:

  1. fmc_psram_set_pad_config_for_psram_power_off(FMC_PSRAM_IDX1, false);
     

  2. app_pmu_handle_ldo_aux2(ENABLE);
     

  3. platform_delay_us(150);
     

  4. watch_wb_opi_psram_init();
     

Power Consumption Chart

The power consumption of PSRAM in different modes measured under DLPS state is organized as follows:

PSRAM Power Consumption

PSRAM Mode	Refresh Partial Setting	Current(uA)	PSRAM Mode	Refresh Partial Setting	Current(uA)	PSRAM Mode	Current(uA)
Standby	Full Array	40	Hybrid Sleep	Full Array	18	Deep power down	0.2
Standby	Bottom 1/2 Array	37	Hybrid Sleep	Bottom 1/2 Array	15	ldo_aux2 power down	0
Standby	Bottom 1/4 Array	35	Hybrid Sleep	Bottom 1/4 Array	13
Standby	Bottom 1/8 Array	34	Hybrid Sleep	Bottom 1/8 Array	12
Standby	Top 1/2 Array	37	Hybrid Sleep	Top 1/2 Array	14
Standby	Top 1/4 Array	35	Hybrid Sleep	Top 1/4 Array	13
Standby	Top 1/8 Array	34	Hybrid Sleep	Top 1/8 Array	12

ESD Environment PSRAM Interference Issue

• HW Recommended Handling Method

  1. Ensure the single board GND and the chassis metal are reliably connected, it is recommended to use conductive cloth for multi-point connection.

  2. 5V input needs to add TVS, it is recommended to choose a clamping voltage below 10V.

  3. It is recommended to add an overvoltage protection circuit to the 5V input circuit.

• SW Recommended Recovery Process

  During ESD static testing, there is a certain probability that the register settings and data of the built-in PSRAM in the chip will be affected. In case of abnormal data (Note the situations in the "Note"), recovery can be done through the following process:

  1. Call fmc_psram_wb_set_initial_latency(FMC_PSRAM_IDX_TYPE idx) to reset the registers. This is suitable when static electricity only damages the registers, which will also affect the read data. In this case, after resetting the registers, the correct data can be read.

  2. If the data is still abnormal after resetting the registers, it is necessary to rewrite the PSRAM.

  Note

  If using CPU to read, fmc_psram_wb_set_initial_latency() should be called followed by SCB_InvalidateDCache() to avoid fetching the currently affected incorrect data from the internal cache next time; If using DMA to directly transfer data from PSRAM, it is not necessary.