GDMA
Sample List
This chapter introduces the details of the GDMA sample. The RTL87x2G provides the following samples for the GDMA peripheral.
Functional Overview
GDMA is used to provide high-speed data transfer between peripherals and memory or between memory and memory. The data transfer can be done independently of the CPU to reduce the CPU overhead.
GDMA consists of several independent channels, which can transfer data from one place to another. Transfer source and destination can be memory or supported peripherals. A set of Hardware handshake signals connect the peripheral with GDMA, which is used to control the transaction between them. Single transaction and burst transaction are both supported. Transfer data width is also programmable. GDMA is capable of working as a flow controller that determines the length of a GDMA block transfer and terminates the transfer. GDMA transfer can work as a single block or multi-block. Linked lists multi-block and auto-reloading multi-block are both supported. GDMA channel will be disabled automatically after transfer completion. Transfer procedure can be suspended and resumed. If resume is not desired, manually aborting the transfer procedure is supported as well. The GDMA controller has an arbitrator to coordinate the priority of each GDMA request.
Feature List
Number of channels: 10
Programmable GDMA channel priority (priority 0~9)
Hardware handshake for peripheral GDMA transfer.
Support transfer abort/suspend function.
Support single transaction and burst transaction.
Programmable source and destination addresses for each channel.
Support single-block and multi-block transfer.
Support 2 multi-block functions: auto-reloading and linked list.
Programmable transfer type for each channel: memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral.
Programmable Block size 1 to 65535 items (item size = Transfer data width).
Support transfer data width: byte (8 bits), half-word (16 bits), word (32 bits).
Support transfer complete interrupt and block transfer complete interrupt.
Note
GDMA0_channel9 is designated as LOG UART, while in HCI Mode, GDMA0_channel1 is designated as HCI UART TX, and GDMA0_channel2 as HCI UART RX. Be cautious to avoid resource conflicts during use.
Transfer Type
GDMA supports four types of transfers: memory to memory, memory to peripheral, peripheral to memory, and peripheral to peripheral.
These can be configured using GDMA_InitTypeDef::GDMA_DIR.
Under the four types of transfers, different settings are usually applied to the source and destination addresses.
If the source or destination address is memory, it is generally set to increment;
if the source or destination address is a peripheral’s FIFO, it is generally set to fixed.
The specific settings need to be chosen by the user based on the actual situation.
The changes in the source and destination addresses can be configured using GDMA_InitTypeDef::GDMA_SourceInc and GDMA_InitTypeDef::GDMA_DestinationInc.
Hardware Handshake
Hardware handshake is supported in GDMA, which conforms to a protocol and handshakes between GDMA and source or destination peripheral in order to control transferring a single or burst transaction between them.
If the peripheral is the source side of GDMA, hardware handshake should be set. The source handshake is set through GDMA_InitTypeDef::GDMA_SourceHandshake.
If the peripheral is the destination side of GDMA, hardware handshake should be set. The destination handshake is set through GDMA_InitTypeDef::GDMA_DestHandshake.
The hardware handshakes supported by GDMA can be referenced in GDMA Handshake Type.
Transaction
A transaction is the basic unit for GDMA transfers, representing the amount of data handled by the GDMA each time it is triggered.
Transactions are configured via GDMA_InitTypeDef::GDMA_SourceMsize and GDMA_InitTypeDef::GDMA_DestinationMsize.
GDMA transactions are divided into the following two types:
Single transaction: Length of a single transaction is always 1 and is converted to a single transfer, corresponding to setting
GDMA_InitTypeDef::GDMA_SourceMsizetoGDMA_Msize_1.Burst transaction: Length of a burst transaction is programmed into the GDMA.
The setting of Burst transaction is usually related to the FIFO size of the source or destination peripheral. Generally speaking, the larger the Burst transaction Size is set, the faster the GDMA transfer efficiency. For some peripherals, when the rate is relatively high, it is not recommended to use Single transaction (for example, SPI). Due to the relatively low efficiency of Single transaction, it may cause Tx underflow in the case of SPI TX + GDMA.
GDMA Block Transfer
GDMA supports single-block and multi-block transfers.
Single-block: The GDMA data length consists of only one block. When the GDMA transfer is complete, it will trigger the GDMA total transfer complete
GDMA_INT_Transferinterrupt.Multi-block: The GDMA data length consists of multiple blocks. After the end of the previous block, a new block transfer will automatically start. A block transfer complete
GDMA_INT_Blockinterrupt will be triggered after each block transfer is completed.
The size of a single block is set by GDMA_InitTypeDef::GDMA_BufferSize. The maximum data size of a single block is 65535. If the total amount of data to be transferred by GDMA exceeds 65535, the multi-block mode must be used for the transfer.
During initialization, multi-block transfer is enabled by setting GDMA_InitTypeDef::GDMA_Multi_Block_En to ENABLE.
Multi-block Transfer Mode
Multi-block transmission supports two modes: Linked Lists and Auto-reloading, which can be set through the initialization structure parameter GDMA_InitTypeDef::GDMA_Multi_Block_Mode.
For both source and destination transmissions, the above two modes are supported, so in Multi-block mode, it can be further divided into the following seven transmission modes:
Multi-block Mode |
Brief |
|---|---|
Auto-Reload destination address with continuous source address |
|
Auto-Reload source address with continuous destination address |
|
Auto-Reload source address and destination address |
|
LLI destination address with continuous source address |
|
LLI destination address with auto-Reload source address |
|
LLI source address with continuous destination address |
|
LLI source address with auto-Reload destination address |
|
LLI source address and destination address |
Linked Lists
Linked list pointer (LLP) points to the location in system memory where the next linked list item (LLI) exists. The LLI is a set of registers that describes the next block (block descriptor) and an LLP register. The GDMA fetches the LLI at the beginning of every block when block chaining is enabled.
In multi-block transfer with linked lists for source and destination, GDMA is enabled by software which starts the block transfer. GDMA fetches the LLI and reprograms the channel registers according to LLI. Then GDMA block transfer starts. GDMA reads the source and destination status and writes them back to the corresponding position of LLI. After the block transfer, GDMA detects whether LLP and auto-reloading bit of source and destination are all set to 0, which means the whole GDMA transfer has been finished, GDMA transfer complete interrupt will be triggered if it is unmasked. Otherwise it means that one of the blocks has been finished and another block will be started automatically after GDMA fetch another LLI.
In the Linked List transfer mode, after each Block is transmitted, it is necessary to reload the GDMA settings from the LLI into the GDMA registers. Therefore, during initialization, the GDMA settings for each Block must be configured in each LLI.
The LLI structure can be configured by initializing the structure parameters GDMA_InitTypeDef::GDMA_Multi_Block_Struct.
The items that need to be configured include the SAR, DAR, CTL_LOW, and CTL_HIGH registers. For specific configuration, please refer to the example code Memory to Memory - Multi Block.
Auto-reloading
In multi-block transfers, the automatic reloading of the source and destination is enabled by the software, initiating block transfer via GDMA. GDMA operates according to the configuration of the channel registers.
After the block transfer is completed, GDMA automatically reloads the channel registers with the values present when the channel was first enabled. GDMA checks if the LLP and auto-reload bits of the source and destination are all set to 0, indicating that the entire GDMA transfer is complete, and if the interrupt is not masked, a GDMA transfer completion interrupt will be triggered. Otherwise, this means one block has been completed, and another block will automatically begin.