SPI
Sample List
This chapter introduces the details of the SPI sample. The RTL87x2G provides the following samples for the SPI peripheral.
Functional Overview
The serial peripheral interface (SPI) allows half/full-duplex, synchronous, serial communication with external devices. The interface can be configured in one of two modes of operations: as a serial master or a serial slave. In master mode, it provides the communication clock (SCK) to the external slave device. For RTL87x2G, SPI0 can be the master or slave, SPI1 is the master.
Feature List
SPI Master Feature List:
Support 4 Clock Mode. (CPOL, CPHA)
Mode 0 (CPOL=0, CPHA=0).
Mode 1 (CPOL=0, CPHA=1).
Mode 2 (CPOL=1, CPHA=0).
Mode 3 (CPOL=1, CPHA=1).
Max SPI0 SCK 50MHz; Max SPI1 SCK 20MHz.
SCK frequency= SPI source clock/N; N is any even value between 2 and 65534.
Supports 4 to 32 bits data frame.
TX FIFO depth 32.
RX FIFO depth 32.
Support GDMA.
SPI Slave Feature List:
Support 4 Clock Mode.(CPOL, CPHA)
Max input SCK 20MHz.
Support 4/8/16 bits data frame.
TX FIFO width 16 bits, depth 64.
RX FIFO width 16 bits, depth 64.
Support GDMA.
Transfer Mode
SPI supports four transmission modes:
Full Duplex Mode
In full duplex mode, both the data transmission and reception logic are active. Therefore, attention must be paid to the logic of data transmission and reception during communication. Configure
SPI_InitTypeDef::SPI_Direction
toSPI_Direction_FullDuplex
.Transmit Only Mode
In transmit only mode, only the transmission logic is active, and the reception logic is inactive; received data will not be stored in the RX FIFO. Configure
SPI_InitTypeDef::SPI_Direction
toSPI_Direction_TxOnly
.Receive Only Mode
In receive only mode, only the reception logic is active, and the transmission logic is inactive. Configure
SPI_InitTypeDef::SPI_Direction
toSPI_Direction_RxOnly
.EEPROM Mode
EEPROM mode is typically used to send opcodes or addresses to EEPROM devices. In EEPROM mode, SPI first sends data until the TX FIFO is empty, then begins receiving data. During data transmission, the reception logic is inactive. During data reception, the transmission logic is inactive. Configure
SPI_InitTypeDef::SPI_Direction
toSPI_Direction_RxOnly
. In EEPROM mode, theSPI_InitTypeDef::SPI_RXNDF
value must be set to determine the quantity of data to be received.
Communication Sequence Diagram
SPI supports 4 clock modes, corresponding to the four cases where CPOL and CPHA are 0 and 1.
Clock Polarity (CPOL) bit sets the polarity of the clock signal in idle state. 0 indicates low level, and 1 indicates high level.
Clock Phase (CPHA) bit sets the edge on which data is captured: 0 indicates the first edge, and 1 indicates the second edge.
The diagrams below illustrate the SPI communication timing for each of the four modes.

SPI Communication Sequence Diagram (CPHA is 0)

SPI Communication Sequence Diagram (CPHA is 1)
SPI Slave
When initializing and selecting the peripheral as SPI0_SLAVE, the SPI will be configured in slave mode. When SPI is configured as a slave, all serial transmissions are initiated and controlled by the serial bus master.
When using the SPI slave, pay attention to the following points:
CPHA and CPOL must be set the same as the master device.
If the SPI slave is to transmit data to the master, ensure that there is data in the TX FIFO before the serial master initiates the transmission. If the master initiates a transmission to the SPI slave without data in the slave’s TX FIFO, the SPI status flag
SPI_FLAG_TXE
will be set.After the slave sends the last data frame and the TX FIFO becomes empty, the SPI master should not send clock requests for data from the slave, as the slave has no data to transmit. If the master continues to send clocks at this time, a TX FIFO underflow will occur, triggering the
SPI_INT_TUF
interrupt. The slave will repeatedly return a low level to the master.When the device is operating at high speed, it is recommended to use GDMA for transmission.
SPI High Speed Mode
SPI0 supports high-speed mode. When the SPI transmission rate exceeds 20MHz, it is recommended to use the high-speed mode of SPI0, and it is also recommended to use it with GDMA. In high-speed mode, the peripheral base address should be selected as SPI0_HS.
SPI GDMA
SPI GDMA TX
During the SPI serial transmission process, when the amount of data in the TX FIFO is less than or equal to the value set in the initialization SPI_InitTypeDef::SPI_TxWaterlevel
, a GDMA burst transfer will be triggered.
One GDMA burst transaction will write GDMA_InitTypeDef::GDMA_DestinationMsize
pieces of data into the SPI TX FIFO.
When using SPI GDMA TX, it is recommended to set the value of SPI_InitTypeDef::SPI_TxWaterlevel
to SPI_TX_FIFO_SIZE - MSize
.

SPI GDMA TX Diagram
SPI GDMA RX
During the SPI serial transmission process, when the amount of data in the RX FIFO is greater than or equal to the value set in the initialization for SPI_InitTypeDef::SPI_RxWaterlevel
+ 1, a GDMA burst transfer will be triggered.
One GDMA burst transaction will receive GDMA_InitTypeDef::GDMA_SourceMsize
pieces of data from the SPI RX FIFO.
When using SPI GDMA RX, it is recommended to set the value of SPI_InitTypeDef::SPI_RxWaterlevel
to MSize - 1
.

SPI GDMA RX Diagram