GDMA

GDMA Demo Code Support List

This chapter introduces the details of the GDMA demo code.

GDMA Demo for Memory to Memory Mode

The description of GDMA demo code 1 is shown in the following table.

GDMA Demo Code 1 Description

Demo 1

gdma_demo.c

Sample Purpose

Demonstrate memory to memory by GDMA.

Brief Introduction

This sample code demonstrates memory to memory by GDMA. The data in GDMA_SendBuffer is transferred to GDMA_RecvBuffer.

File Path

sdk\src\sample\io_demo\gdma\memtomem\gdma_demo.c

Function Entry

gdma_demo()

GDMA DIR

GDMA_DIR_MemoryToMemory

GDMA BufferSize

100

GDMA SourceInc

DMA_SourceInc_Inc

GDMA DestinationInc

DMA_DestinationInc_Inc

GDMA SourceDataSize

GDMA_DataSize_Byte

GDMA DestinationDataSize

GDMA_DataSize_Byte

GDMA SourceMsize

GDMA_Msize_1

GDMA DestinationMsize

GDMA_Msize_1

GDMA SourceAddr

GDMA_SendBuffer

GDMA DestinationAddr

GDMA_RecvBuffer

Expected Result

  1. Press the Reset button on the EVB.

  2. The data in GDMA_RecvBuffer is the same as in GDMA_SendBuffer.

GDMA Demo for Multi-Block Mode

The description of GDMA demo code 2 is shown in the following table.

GDMA Demo Code 2 Description

Demo 2

dma_multiblock_demo.c

Sample Purpose

Demonstrate how GDMA multi-block function works.

Brief Introduction

This sample code demonstrates how GDMA multi-block function works. The data in GDMA_SendBuffer is transferred to GDMA_RecvBuffer.

File Path

sdk\src\sample\io_demo\gdma\multiblock\dma_multiblock_demo.c

Function Entry

dma_multiblock_demo()

GDMA DIR

GDMA_DIR_MemoryToMemory

GDMA BufferSize

100

GDMA SourceInc

DMA_SourceInc_Inc

GDMA DestinationInc

DMA_DestinationInc_Inc

GDMA SourceDataSize

GDMA_DataSize_Byte

GDMA DestinationDataSize

GDMA_DataSize_Byte

GDMA SourceMsize

GDMA_Msize_1

GDMA DestinationMsize

GDMA_Msize_1

GDMA SourceAddr

GDMA_SendBuffer

GDMA DestinationAddr

GDMA_RecvBuffer

GDMA Multi-Block Mode

LLI_TRANSFER

Expected Result

  1. Press the Reset button on the EVB.

  2. The data in GDMA_RecvBuffer is the same as in GDMA_SendBuffer.

GDMA Demo for Scatter/Gather Mode

The description of GDMA demo code 3 is shown in the following table.

GDMA Demo Code 3 Description

Demo 3

dma_scrgar_demo.c

Sample Purpose

Demonstrate memory to memory transfer by scatter/gather GDMA.

Brief Introduction

This sample code demonstrates how GDMA scatter/gather function works. The data in GDMA_SendBuffer_5 is transferred to GDMA_RecvBuffer_5.

File Path

sdk\src\sample\io_demo\gdma\multiblock\dma_scrgar_demo.c

Function Entry

dma_scrgar_demo()

GDMA DIR

GDMA_DIR_MemoryToMemory

GDMA BufferSize

20

GDMA SourceInc

DMA_SourceInc_Inc

GDMA DestinationInc

DMA_DestinationInc_Inc

GDMA SourceDataSize

GDMA_DataSize_Byte

GDMA DestinationDataSize

GDMA_DataSize_Byte

GDMA SourceMsize

GDMA_Msize_1

GDMA DestinationMsize

GDMA_Msize_1

GDMA SourceAddr

GDMA_SendBuffer_5

GDMA DestinationAddr

GDMA_RecvBuffer_5

GDMA Scatter Mode

ENABLE

GDMA Scatter Count

4

GDMA Scatter Interval

4

Expected Result

  1. Press the Reset button on the EVB.

  2. The data in GDMA_SendBuffer_5 is transferred to GDMA_RecvBuffer_5 in 4-byte packets and with 4-byte intervals.

UART Demo for RX Data in GDMA Mode

The description of GDMA demo code 4 is shown in the following table.

GDMA Demo Code 4 Description

Demo 4

uart_rx_dma.c

Sample Purpose

Demonstrate how UART receives data by GDMA.

Brief Introduction

This sample code demonstrates the communication between chip and PC. PC transmits some data to chip.

File Path

sdk\src\sample\io_demo\gdma\uart_idle_rx\uart_rx_dma.c

Function Entry

uart_rx_dma()

Hardware Connection

As shown in GDMA Demo Code 4/5 Hardware Connection Diagram.

RTL87x3E: On EVB, TX is connected to M3_0, RX is connected to M3_1, FT_VIO is connected to VIO1, and CON3 is connected to PC.

RTL87x3D: On EVB, TXD is connected to M3_0, RXD is connected to M3_1, FT_VIO is connected to VIO1, and P2 is connected to PC.

UART TX Pin Definition

#define UART_TX_PIN P3_1

UART RX Pin Definition

#define UART_RX_PIN P3_0

UART ID

UART0

Baud Rate

3000000

Parity Check

No parity

Data Format

8-Bit

Stop Bit

1-Bit

Hardware Flow Control

None

Expected Result

  1. Press the Reset button on the EVB, string ### Welcome to use RealTek Bumblebee ###\r\n will be displayed in UART debug tool.

  2. Use UART debug tool to send data to chip, then data will be stored in array uart_receive_buf.

The hardware connection of GDMA demo code 4 is shown in the figure below.

../../../_images/UART_Demo_1_2_3_5_Hardware_Connection_Diagram.png

GDMA Demo Code 4/5 Hardware Connection Diagram

UART Demo for TX Data in GDMA Mode

The description of GDMA demo code 5 is shown in the following table.

GDMA Demo Code 5 Description

Demo 5

uart_tx_gdma.c

Sample Purpose

Demonstrate how UART sends data by GDMA.

Brief Introduction

This sample code demonstrates the communication between chip and PC. Chip transmits some data to PC.

File Path

sdk\src\sample\io_demo\gdma\uart_tx\uart_tx_gdma.c

Function Entry

uart_tx_gdma()

Hardware Connection

As shown in GDMA Demo Code 4/5 Hardware Connection Diagram.

RTL87x3E: On EVB, TX is connected to M3_0, RX is connected to M3_1, FT_VIO is connected to VIO1, and CON3 is connected to PC.

RTL87x3D: On EVB, TXD is connected to M3_0, RXD is connected to M3_1, FT_VIO is connected to VIO1, and P2 is connected to PC.

UART TX Pin Definition

#define UART_TX_PIN P3_1

UART RX Pin Definition

#define UART_RX_PIN P3_0

UART ID

UART0

Baud Rate

115200

Parity Check

No parity

Data Format

8-Bit

Stop Bit

1-Bit

Hardware Flow Control

None

Expected Result

Press the Reset button on the EVB, string ### Welcome to use RealTek Bumblebee ###\r\n will be displayed in UART debug tool.

ADC Demo for GDMA Mode

The description of GDMA demo code 6 is shown in the following table.

GDMA Demo Code 6 Description

Demo 6

adc_gdma_demo.c

Sample Purpose

Demonstrate how ADC samples data in continuous mode by GDMA.

Brief Introduction

Use continuous mode of ADC peripheral to measure voltage on P0_0 and P0_1.

File Path

sdk\src\sample\io_demo\gdma\adc_dma\adc_gdma_demo.c

Function Entry

adc_gdma_demo()

Pre-Condition

Turn off Charger auto enable and Battery detection support on the MCUConfig Tool.

Channel

ADC0

ADC1

External Channel Input Mode

ADC0 and ADC1 are divide mode.

Hardware Connection

Connect M0_0 and M0_1 of EVB to external DC voltage source. Input voltage of M0_0 and M0_1 must range from 0 to 3.3V.

Expected Result

Press the Reset button on the EVB, ADC starts continuous sampling, and sample rawdata will be stored in array ADC_Buffer.

I2C Demo for GDMA Mode

The description of GDMA demo code 7 is shown in the following table.

GDMA Demo Code 7 Description

Demo 7

i2c_dma_demo.c

Sample Purpose

Demonstrate how I2C master and slave work in GDMA mode.

Brief Introduction

This sample code demonstrates the communication between I2C master and slave in GDMA mode. Master will read data from slave.

File Path

sdk\src\sample\io_demo\gdma\i2c_dma\MasterRx+SlaveTx\i2c_dma_demo.c

Function Entry

i2c_dma_demo()

Hardware Connection

As shown in GDMA Demo Code 7 Hardware Connection Diagram. On EVB, connect P0_0 to P1_0, connect P0_1 to P1_1.

I2C Master SCL Pin Definition

#define I2C1_SCL P0_1

I2C Master SDA Pin Definition

#define I2C1_SDA P0_0

I2C Slave SCL Pin Definition

#define I2C0_SCL P1_1

I2C Slave SDA Pin Definition

#define I2C0_SDA P1_0

I2C Master ID

I2C1

I2C Slave ID

I2C0

Clock Speed

400000

Address Mode

7-Bit

Slave Address

0x50

ACK

ACK enable

GDMA DIR

Master: GDMA_DIR_PeripheralToMemory

Slave: GDMA_DIR_MemoryToPeripheral

GDMA BufferSize

#define TEST_SIZE 255

GDMA SourceInc

Master: DMA_SourceInc_Fix

Slave: DMA_SourceInc_Inc

GDMA DestinationInc

Master: DMA_DestinationInc_Inc

Slave: DMA_DestinationInc_Fix

GDMA SourceDataSize

Master: GDMA_DataSize_Byte

Slave: GDMA_DataSize_HalfWord

GDMA DestinationDataSize

Master: GDMA_DataSize_Byte

Slave: GDMA_DataSize_HalfWord

GDMA SourceMsize

GDMA_Msize_4

GDMA DestinationMsize

GDMA_Msize_4

GDMA SourceAddr

Master: &(I2C1->IC_DATA_CMD)

Slave: sendbuf

GDMA DestinationAddr

Master: readbuf

Slave: &(I2C0->IC_DATA_CMD)

GDMA SourceHandshake

Master: GDMA_Handshake_I2C1_RX

GDMA DestHandshake

Slave: GDMA_Handshake_I2C0_TX

Expected Result

  1. Press the Reset button on the EVB.

  2. Strings i2c0_handler: I2C_INT_RD_REQ, i2c_tx_dma_handler, i2c_rx_dma_handler, i2c1_handler: I2C1 stop detect will be displayed in Debug Analyzer in order.

The hardware connection of GDMA demo code 7 is shown in the figure below.

../../../_images/I2C_GDMA_Hardware_Connection_Diagram.png

GDMA Demo Code 7 Hardware Connection Diagram

GDMA Demo for DLPS Recover

The description of GDMA demo code 8 is shown in the following table.

GDMA Demo Code 8 Description

Demo 8

dlps_gdma_recover_demo.c

Sample Purpose

Demonstrate how GDMA recovers from DLPS.

Brief Introduction

This sample code demonstrates how GDMA recovers from DLPS. The UART can receive data through GDMA when the chip wakes up from DLPS.

File Path

sdk\src\sample\io_demo\dlps\dlps_gdma_recover_demo.c

Function Entry

dlps_gdma_recover_demo()

Hardware Connection

As shown in GDMA Demo Code 8 Hardware Connection Diagram. RTL87x3E: On EVB, TX is connected to M3_0, RX is connected to M3_1, FT_VIO is connected to VIO1, CON3 is connected to PC, and wake up pin is connected to P0_0. RTL87x3D: On EVB, TXD is connected to M3_0, RXD is connected to M3_1, FT_VIO is connected to VIO1, P2 is connected to PC, and wake up pin is connected to P0_0.

UART TX Pin Definition

#define UART_TX_PIN P3_1

UART RX Pin Definition

#define UART_RX_PIN P3_0

UART ID

UART0

Baud Rate

3000000

Parity Check

No parity

Data Format

8-Bit

Stop Bit

1-Bit

Hardware Flow Control

None

Expected Result

  1. Press the Reset button on the EVB, string ### Welcome to use RealTek Bumblebee ###\r\n will be displayed in UART debug tool.

  2. Use UART debug tool to send data to chip, then data will be stored in array uart_receive_buf.

The hardware connection of GDMA demo code 8 is shown in the figure below.

../../../_images/GDMA_Recover_From_DLPS_Hardware_Connection_Diagram.png

GDMA Demo Code 8 Hardware Connection Diagram

SPI Demo for GDMA Mode

The description of GDMA demo code 9 is shown in the following table.

GDMA Demo Code 9 Description

Demo 9

spi_dma_demo.c

Sample Purpose

Demonstrate how SPI sends and receives data in master mode by GDMA.

File Path

sdk\src\sample\io_demo\gdma\spi_dma\spi_dma_demo.c

Function Entry

spi_dma_demo()

Hardware Connection

As shown in GDMA Demo Code 9 Hardware Connection Diagram. Connect M0_1 to CS of SPI slave device, connect M0_0 to SCK of SPI slave device, connect M1_0 to MISO of SPI slave device, and connect M1_1 to MOSI of SPI slave device.

SPI CS Pin Definition

#define PIN_SPI1_CS P0_1

SPI SCK Pin Definition

#define PIN_SPI1_SCK P0_0

SPI MOSI Pin Definition

#define PIN_SPI1_MOSI P1_0

SPI MISO Pin Definition

#define PIN_SPI1_MISO P1_1

SPI ID

SPI1

Mode

Master

Speed

400000

Data Size

8-Bit

Expected Result

  1. Press the Reset button on the EVB, the data in array sendbuf is sent to SPI slave device and prints the string spi_tx_dma_handler in the Debug Analyzer.

  2. After the slave device receives the data, the slave device sends data to the chip, the chip stores the received data in array readbuf and prints the string spi_rx_dma_handler in the Debug Analyzer.

The hardware connection of GDMA demo code 9 is shown in the figure below.

../../../_images/SPI_Demo_4_Hardware_Connection_Diagram.png

GDMA Demo Code 9 Hardware Connection Diagram

Functional Overview

GDMA is used to provide high-speed data transfer between peripherals and memory or between memory and memory. The data transfer can be done independently of the CPU to reduce the CPU overhead.

Each channel of the GDMA controller can handle requests from one or more peripherals for memory access. The GDMA controller has an arbitrator to coordinate the priority of each GDMA request.

Feature List

  • Programmable transfer type for each channel: memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral.

  • Programmable source and destination addresses for each channel.

  • Address increment, or fixed.

  • Programmable burst transaction size for each channel.

  • Support transfer abort/suspend function.

  • Programmable channel priority.

  • Independent interrupts and control bit for every channel.

  • Support single-block and multi-block transfer.

  • Support scatter and gather transfer.

Note

RTL87x3D supports 16 channels, if using SPI high-speed mode, please use channel 0 and 1. RTL87x3E supports 9 channels, RTL87x3EP supports 12 channels.

Parameter Significance

  1. GDMA_ChannelNum

    Channel numbers can be 0 to 15.

  2. GDMA_DIR

    The transfer direction can be memory to memory or memory to peripheral or peripheral to memory or peripheral to peripheral.

  3. GDMA_SourceInc

    Indicates whether to increment the source address on every source transfer.

  4. GDMA_DestinationInc

    Indicates whether to increment the destination address on every destination transfer.

  5. GDMA_SourceDataSize

    Source single transaction size in bytes: src_single_size_bytes = GDMA_SourceDataSize

  6. GDMA_DestinationDataSize

    Destination single transaction size in bytes: dst_single_size_bytes = GDMA_DestinationDataSize

  7. GDMA_SourceMsize

    Source burst transaction size in bytes: src_burst_size_bytes = GDMA_SourceMsize * src_single_size_bytes

  8. GDMA_DestinationMsize

    Destination burst transaction size in bytes: dst_burst_size_bytes = GDMA_DestinationMsize * dst_single_size_bytes

  9. GDMA_BufferSize

    The total number of bytes to be transferred in a block is: blk_size_bytes_dma = GDMA_BufferSize * src_single_size_bytes

Note

The above parameter configuration needs to satisfy the following formula:
GDMA_SourceDataSize * GDMA_SourceMsize = GDMA_DestinationDataSize * GDMA_DestinationMsize

Waterlevel Setting

Handshaking interfaces are used at the transaction level to control the flow of single or burst transactions. Waterlevel is mainly divided into TX FIFO waterlevel and RX FIFO waterlevel. When the effective data amount in the FIFO reaches the set value of waterlevel, a burst transmission is initiated. GDMA_SourceMsize, GDMA_DestinationMsize, GDMA_SourceDataSize, GDMA_DestinationDataSize and peripheral waterlevel setting table is presented below.

MSize and Peripheral Waterlevel Setting Table

IO

Dir

Peripheral GDMA waterlevel

GDMA_SourceMsize

GDMA_DestinationMsize

GDMA_SourceDataSize

GDMA_DestinationDataSize

UART

TX

.TxWaterlevel = 12

1

4

Word

Byte

RX

.RxWaterlevel = 4

4

1

Byte

Word

SPI Master

TX

.SPI_TxWaterlevel = 24

4

8

Word

HalfWord

RX

.SPI_RxWaterlevel = 7

8

4

HalfWord

Word

TX

.SPI_TxWaterlevel = 28

1

4

Word

Byte

RX

.SPI_RxWaterlevel = 3

4

1

Byte

Word

SPI Slave

TX

.SPI_TxWaterlevel = 58

1

4

Word

Byte

RX

.SPI_RxWaterlevel = 3

4

1

Byte

Word

I2C

TX

.I2C_TxWaterlevel = 14

4

8

Word

HalfWord

RX

.I2C_RxWaterlevel = 3

4

1

Byte

Word

ADC

.adcBurstSize = 8

8

8

HalfWord

HalfWord

SPI_HS

TX

.SPI_TxWaterlevel = 25

32

32

Byte

Byte

RX

.SPI_RxWaterlevel = 31

32

32

Byte

Byte

Program Examples

Single-Block Transfer Initialization Flow

The initialization flow of GDMA single-block transfer is shown in the following figure.

../../../_images/GDMA_Single-Block_Transfer_Operation_Flow_Chart.png

GDMA Single-Block Transfer Operation Flow Chart

The codes below demonstrate the GDMA single-block transfer.

uint16_t i = 0;
RCC_PeriphClockCmd(APBPeriph_GDMA, APBPeriph_GDMA_CLOCK, ENABLE);
GDMA_InitTypeDef GDMA_InitStruct;

if (!GDMA_channel_request(&mem_to_mem_dma_ch_num, demo_dma_handler, true))
{
   return;
}

/*--------------initialize test buffer---------------------*/
for (i = 0; i < 100; i++)
{
   GDMA_SendBuffer[i] = (i & 0xff);
}
for (i = 0; i < 100; i++)
{
   GDMA_RecvBuffer[i] = 0;
}

GDMA_StructInit(&GDMA_InitStruct);
GDMA_InitStruct.GDMA_ChannelNum      = DEMO_DMA_CHANNEL_NUM;
GDMA_InitStruct.GDMA_DIR             = GDMA_DIR_MemoryToMemory;
GDMA_InitStruct.GDMA_BufferSize      = 100;//determine total transfer size
GDMA_InitStruct.GDMA_SourceInc       = DMA_SourceInc_Inc;
GDMA_InitStruct.GDMA_DestinationInc  = DMA_DestinationInc_Inc;
GDMA_InitStruct.GDMA_SourceDataSize  = GDMA_DataSize_Byte;
GDMA_InitStruct.GDMA_DestinationDataSize = GDMA_DataSize_Byte;
GDMA_InitStruct.GDMA_SourceMsize      = GDMA_Msize_1;
GDMA_InitStruct.GDMA_DestinationMsize = GDMA_Msize_1;
GDMA_InitStruct.GDMA_SourceAddr      = (uint32_t)GDMA_SendBuffer;
GDMA_InitStruct.GDMA_DestinationAddr = (uint32_t)GDMA_RecvBuffer;
GDMA_Init(DEMO_DMA_CHANNEL, &GDMA_InitStruct);

/*-----------------GDMA IRQ init-------------------*/
NVIC_InitTypeDef nvic_init_struct;
nvic_init_struct.NVIC_IRQChannel         = DEMO_DMA_IRQ;
nvic_init_struct.NVIC_IRQChannelCmd      = (FunctionalState)ENABLE;
nvic_init_struct.NVIC_IRQChannelPriority = 3;
NVIC_Init(&nvic_init_struct);

GDMA_INTConfig(DEMO_DMA_CHANNEL_NUM, GDMA_INT_Block, ENABLE);
GDMA_Cmd(DEMO_DMA_CHANNEL_NUM, ENABLE);